The present invention relates generally to the field of integrated circuit processing, and more particularly relates to an FeRAM structure and a method of manufacture thereof having a capacitor stack etch which effectively etches the ferroelectric dielectric layer without degradation thereof.
Several trends exist, today, in the semiconductor device fabrication industry and the electronics industry. Devices are continuously getting smaller and smaller and requiring less and less power. A reason for this is that more personal devices are being fabricated which are very small and portable, thereby relying on a small battery as its supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of all these trends, there is a need in the industry to provide a computational device which has a fair amount of memory and logic functions integrated onto the same semiconductor chip. Preferably, this memory will be configured such that if the battery dies, the contents of the memory will be retained. Such a memory device which retains its contents while a signal is not continuously applied to it is called a non-volatile memory. Examples of conventional non-volatile memory include: electrically erasable, programmable read only memory (xe2x80x9cEEPROMxe2x80x9d) and FLASH EEPROM.
A ferroelectric memory (FeRAM) is a non-volatile memory which utilizes a ferroelectric material, such as SBT or PZT, as the capacitor dielectric situated between a bottom electrode and a top electrode. Both read and write operations are performed for a FeRAM. The memory size and memory architecture affect the read and write access times of a FeRAM. Table 1 illustrates the differences between different memory types.
The non-volatility of an FeRAM is due to the bi-stable characteristic of the ferroelectric memory cell. Two types of memory cells are used, a single capacitor memory cell and a dual capacitor memory cell. The single capacitor memory cell (referred to as a 1T/1C or 1C memory cell) requires less silicon area (thereby increasing the potential density of the memory array), but is less immune to noise and process variations. Additionally, a 1C cell requires a voltage reference for determining a stored memory state. The dual capacitor memory cell (referred to as a 2T/2C or 2C memory cell) requires more silicon area, and it stores complementary signals allowing differential sampling of the stored information. The 2C memory cell is more stable than a 1C memory cell.
As illustrated in prior art FIG. 1, a 1T/1C FeRAM cell 10 includes one transistor 12 and one ferroelectric storage capacitor 14. A bottom electrode of the storage capacitor 14 is connected to a drain terminal 15 of the transistor 12. The 1T/1C cell 10 is read from by applying a signal to the gate 16 of the transistor (word line WL)(e.g., the Y signal), thereby connecting the bottom electrode of the capacitor 14 to the source of the transistor (the bit line BL) 18. A pulse signal is then applied to the top electrode contact (the plate line or drive line DL) 20. The potential on the bit line 18 of the transistor 12 is, therefore, the capacitor charge divided by the bit line capacitance. Since the capacitor charge is dependent upon the bi-stable polarization state of the ferroelectric material, the bit line potential can have two distinct values. A sense amplifier (not shown) is connected to the bit line 18 and detects the voltage associated with a logic value of either 1 or 0. Frequently the sense amplifier reference voltage is a ferroelectric or non-ferroelectric capacitor connected to another bit line that is not being read. In this manner, the memory cell data is retrieved.
A characteristic of the shown ferroelectric memory cell is that a read operation is destructive. The data in a memory cell is then rewritten back to the memory cell after the read operation is completed. If the polarization of the ferroelectric is switched, the read operation is destructive and the sense amplifier must rewrite (onto that cell) the correct polarization value as the bit just read from the cell. This is similar to the operation of a DRAM. The one difference from a DRAM is that a ferroelectric memory cell will retain its state until it is interrogated, thereby eliminating the need of refresh.
As illustrated, for example, in prior art FIG. 2, a 2T/2C memory cell 30 in a memory array couples to a bit line 32 and an inverse of the bit line (xe2x80x9cbit line-barxe2x80x9d) 34 that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The dual capacitor ferroelectric memory cell comprises two transistors 36 and 38 and two ferroelectric capacitors 40 and 42, respectively. The first transistor 36 couples between the bit line 32 and a first capacitor 40, and the second transistor 38 couples between the bit line-bar 34 and the second capacitor 42. The first and second capacitors 40 and 42 have a common terminal or plate (the drive line DL) 44 to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors 36 and 38 of the dual capacitor ferroelectric memory cell 30 are enabled (e.g., via their respective word line 46) to couple the capacitors 40 and 42 to the complementary logic levels on the bit line 32 and the bar-bar line 34 corresponding to a logic state to be stored in memory. The common terminal 44 of the capacitors is pulsed during a write operation to polarize the dual capacitor memory cell 30 to one of the two logic states.
In a read operation, the first and second transistors 36 and 38 of the dual capacitor memory cell 30 are enabled via the word line 46 to couple the information stored on the first and second capacitors 40 and 42 to the bar 32 and the bit line-bar line 34, respectively. A differential signal (not shown) is thus generated across the bit line 32 and the bit line-bar line 34 by the dual capacitor memory cell 30. The differential signal is sensed by a sense amplifier (not shown) that provides a signal corresponding to the logic level stored in memory.
A memory cell of a ferroelectric memory is limited to a finite number of read and write operations before the memory cell becomes unreliable. The number of operations that can be performed on a FeRAM memory is known as the endurance of a memory. The endurance is an important factor in many applications that require a nonvolatile memory. Other factors such as memory size, memory speed, and power dissipation also play a role in determining if a ferroelectric memory is viable in the memory market.
In essence, the instant invention relates to the fabrication of an FeRAM device which is either a stand-alone device or one which is integrated onto a semiconductor chip which includes many other device types. Several requirements either presently exist or may become requirements for the integration of FeRAM with other device types. One such requirement involves utilizing, as much as possible, the conventional front end and back end processing techniques used for fabricating the various logic and analog devices on the chip to fabricate this chip which will include FeRAM devices. In other words, it is beneficial to utilize as much of the process flow for fabricating these standard logic devices (in addition to I/O devices and potentially analog devices) as possible, so as not to greatly disturb the process flow (and thus increase the process cost and complexity) merely to integrate the FeRAM devices onto the chip.
The following discussion is based on the concept of creating the ferroelectric capacitors in a FeRAM process module that occurs between the front end module (defined to end with the formation of W contacts) and the back end process module (mostly metallization). Other locations of the FeRAM process module have also been proposed. For example, if the FeRAM process module is placed over the first layer of metallization then a capacitor over bar structure can be created with the advantage that a larger capacitor can be created. One disadvantage of the approach is that either Metal-1 or a local interconnect must be compatible with FeRAM process temperature (W for example) or the FeRAM process temperature must be lowered to be compatible with standard metallization (Al xcx9c450 C., Cu-Low-K xcx9c400 C). This location has some advantages for commodity memory purposes, but has cost disadvantages for embedded memory applications. Another proposed location for the FeRAM process module is near the end of the back end process flow. The principal advantage of this approach is that it keeps new contaminants in the FeRAM module (Pb, Bi, Zr, Ir, Ru, or Pt) out of more production tools. This solution is most practical if the assumption is that all of the equipment used after deposition of the first FeRAM film must be dedicated and can not be shared. This solution has the drawback of requiring FeRAM process temperatures compatible with standard metallization plus wiring of the FeRAM capacitor to transistor and other needs of metallization are not compatible with a minimum FeRAM cell size.
The requirements for the other locations will have many of the same concerns, but some requirements will be different.
The FeRAM process module must therefore be compatible with front end process flow including the use of W contacts (currently standard in most logic flows) as the bottom contact of the capacitor. The FeRAM thermal budget must also be low enough so that it does not impact the front end structures such as the low resistance structures (such as tungsten plugs and silicided source/drains and gates) required by most logic devices. In addition, transistors and other front end devices such as diodes are sensitive to contamination and the FeRAM process module can not contaminate these devices either directly (diffusion in chip) or indirectly (cross contamination through shared equipment). The FeRAM devices and process module must also be compatible with a standard back end process flow. Therefore the FeRAM process module must have minimum degradation of logic metallization""s resistance and parasitic capacitance between metal and transistor. In addition, the FeRAM devices must not be degraded by the back end process flow with minimal, if any, modification. This is a significant challenge since ferroelectric capacitors have been shown to be sensitive to hydrogen degradation and most logic back end process flows use hydrogen/deuterium in many of the processes (SiO2, Si3N4, and CVD W deposition, SiO2 via etch, and forming gas anneals).
Commercial success of FeRAM also requires minimization of embedded memory cost. Total memory cost is primarily dependent on cell size, periphery ratio size, impact of yield, and additional process costs associated with memory. In order to have a cost advantage per bit compared to standard embedded memories such as embedded DRAM and Flash it is necessary to have cell sizes that are not much larger than these competing technologies. Some of the methods discussed in this patent to minimize cell size is to make the process flow less sensitive to lithography misalignment, have the capacitor directly over the contact, and using a single mask for the capacitor stack etch.
In accordance with one aspect of the present invention, a method of forming an FeRAM capacitor is provided in which a post capacitor stack etch clean/repair procedure is employed. Unlike prior art wet etch solutions that remove damaged PZT material on the capacitor stack PZT sidewall, the present invention repairs PZT etch damage without any substantial removal of PZT material. In doing so, further damage to the PZT layer via potential alteration of the PZT microstructure is avoided. In addition, potential reliability issues relating to undercut of the PZT layer due to wet etch material removal is eliminated. That is, since PZT material suffering etch damage is not removed, but rather is repaired, the subsequent formation of the sidewall diffusion barrier provides a more effective barrier.
In accordance with another aspect of the present invention, a method of performing a post-capacitor stack etch clean/repair is disclosed. The method comprises forming a capacitor stack by etching a top electrode layer, a PZT layer, and a bottom electrode layer using a patterned hard mask. The method further comprises repairing damage to the PZT layer after the capacitor stack etch by controlling the lead activity and therefore the lead composition associated therewith. In one exemplary aspect of the invention, the damage is repaired by exposing, in an elevated thermal environment, the etched capacitor stack to a lead source material with oxygen having a vapor pressure that is greater than the vapor pressure of the damaged PZT material. The Pb overpressure facilitates vapor transport of lead (for example, lead oxide) from the source material to the damaged PZT thereby repairing the etch damage and filling point defects therein.